1. Field of the Invention
The present invention is directed to an inverter power supply providing an output AC power through a coupling transformer for driving a device, and more particularly to an inverter power supply including a self-excited oscillator and operating at a maximum efficiency over a wide range of variations in an input DC voltage.
2. Description of the Related Art
A prior art inverter power supply is proposed in the German Patent Publication DE 42 08 911 A1 (corresponding to U.S. application Ser. No. 848,893). As represented in FIG. 1, the related art power supply comprises an AC-to-DC converter 10' providing a rectified and smoothed DC voltage from AC mains, a transformer 20' having a primary winding 21', a secondary winding 22', and a feedback winding 23', and a self-excited oscillator energized by the DC voltage to generate a high frequency voltage across the primary winding 21' and induce across the secondary winding 22' a resulting output AC voltage for driving a load. The oscillator comprises an FET transistor 31' connected in series with the primary winding 21' across the DC voltage and driven to turn on and off by the high frequency voltage induced across the feedback winding 23'. A biasing capacitor 12' is connected in series with the feedback winding 23' across a source-gate path of FET 31' for providing an offset voltage which is additive to the feedback voltage at the feedback winding 23' to give a bias voltage applied to a gate of FET 31' so as to alternately turn on and off FET for self-excited oscillation of providing the high frequency voltage across the primary winding 21'. In order to prevent FET 31' from being turned on for an extended period in response to an increase in the input DC voltage, a bias stabilizing circuit is introduced in the related art power source. The bias stabilizing circuit comprises a resistor 41' and a bypass diode 42' connected in circuit to lower the offset voltage by discharging the biasing capacitor 12' through FET 31' being turned on, so as to correspondingly lower the bias voltage to the gate of FET 31', thus enabling FET 31' to turn on only for substantially a constant ON-time period irrespective of increase in the input DC voltage. In other words, since the increased input DC voltage will increase the high frequency feedback voltage, the resulting bias voltage has an elongated time period in which the bias voltage exceeds a threshold voltage of FET 31', which in the absence of the above bias stabilizing circuit, would act to extend the ON-period of FET 31' with corresponding increase in a current flowing through FET 31' and therefore bring an undesired switching loss. In this sense, the related art power supply is found satisfactory in minimizing a switching loss and operating efficiently.
The above operation of the bias stabilizing circuit is easily understood with reference to FIGS. 2 and 3 which illustrate waveforms of the bias voltage V.sub.B applied to the gate of FET 31', offset voltage V.sub.OFF, threshold voltage V.sub.TH, and a drain supply voltage V.sub.DD Of FET 31'. FIG. 2 illustrates a condition where the prior power supply operates with the input DC voltage of a regular level. When the DC voltage increases to some extent with a resulting increase in the feedback voltage, the offset voltage V.sub.OFF is correspondingly lowered, as shown in FIG. 4, by the discharging of capacitor 12' through the bias stabilizing circuit of resistor 41' and diode 42' and through FET 31' so as to lower the bias voltage V.sub.B (which is the feedback voltage plus offset voltage V.sub.OFF), thereby preventing the elongation of the ON-period of FET 31' during which the bias voltage V.sub.B exceeds the threshold voltage V.sub.TH. This means that when the input DC voltage increases to momentarily elongate the ON-period of FET 31', the offset voltage V.sub.OFF responds to be lowered in compensation for the increase in the feedback voltage acting in the direction of elongating the ON-period of FET 31' and therefore lower the bias voltage V.sub.B for preventing FET 31' from keeping turned on for an extended ON-period and operating the power supply efficiently irrespective of the increase in the input DC voltage.
However, a problem still exists in this related art power supply in that the bias stabilizing circuit is effective only for a limited range of the input DC voltage increase and fails to lower the bias voltage further in compensation for an increase in the DC voltage beyond the limited range due to the presence of a parasitic diode 32' inherent to FET 31'. That is, when the input DC voltage increases further with an attendant increase in the feedback voltage to such an extent that the ON-period of FET is elongated to make the drain supply voltage V.sub.DD negative relative to the ground level as indicative of that the primary winding 21' induces the voltage greater than the input DC voltage, the parasitic diode 32' constitutes a closed loop of flowing a current caused by such negative voltage through the primary winding 21', the input DC voltage source 10' and the parasitic diode 32', whereby the drain supply voltage V.sub.DD is fixed to around the ground level and is prohibited from going negative. With this result, the offset voltage V.sub.OFF is not allowed to go negative, which means that the bias voltage V.sub.B is not lowered enough to compensate for the increase in the feedback voltage, i.e., in the input DC voltage. Consequently, there appears an extended ON-period in which the bias voltage V.sub.B exceeds the threshold voltage V.sub.TH so as to keep FET 31' turned on for an extend period accompanied with a correspondingly increased drain current I.sub.D through FET 31', as shown in FIG. 4 Thus, the related art power supply fails to operate efficiently and suffers from considerable switching loss when the input DC voltage increases to a great extent. To eliminate the above insufficiency, it may be deemed effective to limit the feedback voltage induced at the feedback winding either by reducing the number of turns thereof or by increasing the number of turns for the primary winding. However, such scheme is found not practical because of that the number of turns of the feedback winding cannot be reduced to less than one turn and that there arises another difficulty in obtaining suitable secondary voltage when the primary winding is designed to have an large number of turns.